Description

DVCon attendees have the opportunity to take part in the many informal, but often intense, technical discussions that pop-up around the conference venue among 800+ design and verification engineers and engineering managers. This networking opportunity among peers is possibly the greatest benefit to DVCon attendees. Finally, DVCon attendees have access to the vendors of advanced design and verification tools, IP/VIP and services who exhibit at the conference.

Schedules

February 27 - March 2, 2017

Frequency

Annual

Venue

Type of event
national trade fair
Open for
Trade visitors
Industry branches
Electronics, Software
Products & Sectors
Hardware design and verification languages. application of languages, Tools and methodologies for the design and verification of electronic systems and integrated circuits. usage of specialized design and verification languages such as verilog, Systemverilog, Vhdl, Psl systemc, E, And vera, As well as general purpose languages such as c and c++. tools and methodologies include the use of testbench automation, Hardware-assisted verification, Hardware / software co-verification, Assertion-based and formal verification, And transaction-level system design and verification

Information for visitors and exhibitors

All exhibitors at a glance

All exhibitors at a glance

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